The invention relates generally to the field of solid state image sensors, specifically imagers referred to as Active Pixel Sensors, (APS), and to providing greater fill factors within APS sensors.
APS are solid state imagers wherein each pixel typically contains a photo-sensing means, reset means, a charge transfer means, a charge to voltage conversion means, and all of part of an amplifier. Prior art APS devices have been operated in a manner where each line, or row, of the imager is selected and then read out using a column select signal (analogous to the selection and reading of a memory device). In prior art devices the connection, or contact, to the various nodes within the pixels of a given row is accomplished on a per pixel basis. This is true even though the pixels exist on the same electrical node within a row (see FIG. 1). Since these contact regions are placed in each pixel, and contact regions typically consume a large amount of pixel area due to the overlap of metal layers required, inclusion of these contact regions in each pixel reduces the fill factor for the pixel because it takes up area that could otherwise be used for the photodetector. This reduces the sensitivity and saturation signal of the sensor. This adversely affects the photographic speed and dynamic range of the sensor, performance measures that are critical to obtaining good image quality. In addition prior art APS pixels have included the entire amplifier, address and reset transistors within a single pixel, and have made operative interconnection of these components and the photodetector entirely within a single pixel boundary. This leads to inefficiencies of layout and produces pixels with small fill factors.
In order to build high resolution, small pixel APS devices, it is necessary to use sub-xe2x96xa1m CMOS processes in order to minimize the area of the pixel allocated to the row select transistor and other parts of the amplifier in the pixel. In essence, it takes a more technologically advanced and more costly process to realize the same resolution and sensitivity in an APS device as compared to a standard charge coupled device (CCD) sensor. However, APS devices have the advantages of single 5V supply operation, lower power consumption, x-y addressability, image windowing, and the ability to effectively integrate signal processing electronics on-chip, when compared to CCD sensors.
A typical prior art APS pixel 10 is shown in FIG. 1. The pixel comprises a photodetector (PDET) 11, that can be either a photodiode or photogate, a transfer gate (TG) 12, floating diffusion (FD) 14, reset transistor with a reset gate (RG) 16, row select transistor with a row select gate (RSG) 4, and signal transistor (SIG) 5. Note that all of the electrical components required to readout and address the pixel are contained entirely within a single pixel boundary, and are operatively connected entirely within a single pixel boundary. Regions to provide contact to each of the various electrical nodes within the pixel that are common to a row are designated in FIG. 1 and shown schematically in FIG. 2. These are Transfer Gate Contact (TGC) 13, Reset Gate Contact (RGC) 17, and Row Select Gate Contact (RSGC) 3. Additionally there are contact regions that are common to a column. These are also shown in FIGS. 1 and 2. These are power supply contacts (VDDC) 9 and the pixel output node contact (OUTC) 8. Note that there are separate and individual contact regions in each pixel even though some are common to a row or column. It is evident that the area consumed by these contact regions is a significant portion of the pixel area, thus limiting the area available for the photodetector, which reduces the fill factor and sensitivity of the pixel.
It should be apparent, from the foregoing discussion, that there remains a need in the art for APS sensors that have increased fill factors. This and other problems are addressed by the present invention.
The present invention addresses the foregoing problems. Briefly summarized, according to one aspect of the present invention the an image sensor having a plurality of pixels comprising: a semiconductor material of a first conductivity type; and at least two adjacent pixel having photodetectors formed within the substrate such that each pixel has at least one electrical function that is shared by the adjacent pixels.
The pixel layout innovation provided by the present invention yields a higher fill factor for the pixel. One approach to providing an image sensor with the sensitivity of a CCD and the advantages of an APS device is to improve the fill factor, thereby, increasing the corresponding sensitivity of the APS device. This is accomplished by the present invention in several ways: first by eliminating the need for a separate signal line contact areas in each pixel. Secondly, by sharing electrical components between pixels. Finally, fill factor can be increased by operatively interconnecting the electrical components by traversing pixel boundaries and using the array to complete the routing. These are all accomplished while maintaining the ability to selectively address specific pixels of the APS device.
The invention provides a means for reducing the area per pixel required for these contact regions. Conceptually, it can be described in the following manner. The design of each pixel is done to place the contact regions of the row related nodes along or near the left and right edges of the pixel, and the column related contact regions along or near the top or bottom edge of the pixel, (see FIG. 3), allowing neighboring pixels to share these contact regions and alleviating the requirement of having separate contact regions in each pixel. In the case of the preferred embodiment of the present invention, contact regions are required for every 2 pixels as compared to each pixel as required by prior art devices. Hence, the area required per pixel by the present invention is reduced, resulting in an increase in fill factor for the pixel.
Additionally, one can use the VDD drain region of an adjacent pixel as a lateral overflow drain. This is a similar xe2x80x9cpixel sharingxe2x80x9d concept where the VDD drain region serves as the drain of the signal transistor for one pixel and the lateral overflow drain for the adjacent pixel or pixels. Since a separate lateral overflow drain region is not needed for each pixel, more area can be allocated to the photodetector, providing increased fill factor.
Another means to realize fill factor improvement is to utilize the row at a time read out operation, and provide a floating diffusion and amplifier for every two pixels instead of for each pixel. Since only one row is read out at a given time, a single floating diffusion and amplifier can be used for 2 adjacent pixels that are in separate rows. Once again the photodetector area per pixel can be increased, or the fill factor can be maintained to produce a smaller pixel.
Finally, by operatively interconnecting the pixel components such that the components orientation traverse pixel boundaries (rather than providing a schematically complete layout within a single pixel boundary) layout efficiencies can be utilized to improve the fill factor of the pixel.
These and other aspects, objects, features, and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
The present invention has the following advantages. All of the features and advantages of prior art APS devices are maintained while requiring less pixel area for contact regions. This provides the following advantages:
higher fill factor, sensitivity and saturation signal for the same pixel size;
smaller pixel and device size for the same fill factor.